1. Field of the Invention
The present invention relates in general to new and improved systems for preserving critical data from destruction by the adverse effects of an externally originated transient condition and in particular to apparatus and method for providing enhanced reliability of temporary data storage upon exposure to such a condition.
2. Description of the Prior Art
The advanced state of the art of miniaturization and of large scale integration permits present day electronic data processing systems and other equipment using temporary data storage to be incorporated into the machines or devices controlled by such computers. Thus, in many applications the computer, or similar equipment, is subjected to the same ambient conditions as the computer-controlled device. Some of these ambient conditions, although of a transient nature, are capable of producing adverse effects, e.g. in the form of a large power surge in the computer equipment, that may temporarily degrade the performance parameters of the equipment and/or cause temporary equipment failure through a power outage, or otherwise. While the transient condition may have a duration on the order of nanoseconds, the adverse effects may last as long as 5.5 milliseconds. These adverse effects may be directly responsible for the loss of the data in temporary storage. Such data may also be lost indirectly, if the computation process in the associated data processing system is disturbed. For example, there may be a loss of synchronization, or the time reference may be lost. Any one of these effects may impair the integrity of the computed values and may, under worst case conditions, produce failure of the data processing system.
Among the many and diverse tasks commonly performed by present day data processing systems are computations that involve time-dependent data. Any interruption or impairment of the computation process, such as may be caused by the aforesaid transient conditions, will produce errors of the calculated values.
Although integration routines to compensate for system down time have been developed, they are contingent upon the maintenance of an accurate time reference in the computer memory, generally by means of counting the output cycles of an extremely stable oscillator. The time reference serves as the basis for all other integrations and much of the data in the computer is critically dependent thereon. Accordingly, in order to preserve the integrity of such data, it is of vital importance that the integrity of the time reference be maintained throughout the disturbance, or that it be restored following the disturbance.
At the present state of the art, the optimum resolution with which time keeping can be carried out under the conditions described above, ranges from 0.1 to 5.0 msec. Thus, a significant time error may be incurred whenever a power outage, or a similar adverse effect, results from exposure of the computer to the transient condition. In all such cases the computed, time-dependent values will incur comparable errors.
When a data processing system is called on to perform tasks of the type described, time-dependent data values, such as integrals of position, velocity and acceleration which must be updated many times each second, are generally maintained in temporary storage. The temporary data storage device typically comprises a scratch pad memory having a random access capability. Data of a more permanent nature, e.g. a computer program, is normally stored in permanent data storage devices such as ROM's or the like. While the latter storage devices can be adapted by the use of state-of-the-art techniques to withstand the adverse effects of the aforesaid transient condition, temporary data storage devices are, by their nature, more susceptible to a temporary malfunction brought about by these effects. Attempts to lessen their vulnerability to such conditions have met with many difficulties.
For example, random access plated wire memories have achieved a relatively high degree of data retentivity. Such devices are, however, costly to manufacture because of the criticality of component and circuit parameters and because of the relatively large number of parts involved. Further, plated wire memories are subject to unwanted side effects. For example, the transient power surge that may be produced by the aforesaid transient condition may induce stray currents due to circuit imbalances. These currents will circulate in the plated wire matrix where they induce magnetic fields which may upset the memory cells. Memory upset also may occur as a result of spurious write currents caused by such stray currents, or as a result of spurious computer input signals if the data processing system is adversely affected by the transient condition. Any of these effects, when they occur, may cause the data in temporary storage to be scrambled or lost. Accordingly, a great deal of design effort has been expended in the past in an attempt to minimize or eliminate these effects. Notwithstanding these efforts, the magnitude of the problems which remain to be solved lessens the desirability of using plated wire memories at the present stage of development of the art.
A further disadvantage of plated wire memories lies in their relatively slow read and write rates. These may typically range between 0.5 and 1.0 words per msec. For many applications such data transfer rates result in intolerably slow speeds of computation which preclude the use of plated wire memories for the intended purpose.